1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a flash memory device for increasing a threshold voltage of an unselected cell by providing a ground voltage to a source line of a selected cell and supplying a preset voltage to a source line of the unselected cell. The present invention thereby compensates a decrease of the threshold voltage of the unselected cell due to a drain coupling caused by a drain voltage supplied to a bit line of the selected cell.
2. Description of the Background Art
FIGS. 1A-1B are schematic views of a flash memory device of the background art. FIG. 2 is an operational timing diagram of the conventional flash memory device shown in FIGS. 1A-1B. Referring to FIG. 1A, a conventional flash memory device includes a NOR-type flash memory cell array 10, a decoding unit for controlling word lines of cells in the cell array 10 and a multiplexor 30 for controlling bit lines and source lines of the cells.
As shown in FIG. 1A, the decoding unit includes a plurality of decoding blocks 20_1 to 20_j according to predecoder signals XPREA and XPREB inputted thereto, each decoding block having an identical configuration with each other. For example, the first decoding block 20_1 includes a multiplicity of decoding circuits 21_1 to 21_i and each decoding circuit is provided with a first supply voltage VPPX of a positive high voltage, a reset signal XRST and a second supply voltage VEEX of a negative high voltage.
Referring to FIG. 1B, a second decoding circuit 21_2 of the decoding block 20_1 is shown in detail. Since the configuration and the operation of the second decoding circuit 21_2 are identical to those of other decoding circuits in the decoding blocks 20_1 to 20_j, only the operation and configuration of the second decoding circuit 21_2 shown in FIG. 1B will be described hereinafter. It will be understood that the operation and configuration of the remaining decoding circuits will be the same as that described for the second decoding circuit 21_2 which is coupled with a first predecoder signal XPREA1.
As described in FIG. 1B, a first PMOS transistor P11 is connected between a third supply voltage node Vcc and a first node Q11 and is driven in response to the reset signal XRST. A first NMOS transistor N11, a fourth NMOS transistor N14 and a fifth NMOS transistor N15 are connected in series between the first node Q11 and a ground node Vss. The fourth and the fifth NMOS transistors N14, N15, respectively, operate in response to a second predecoder signal XPREB0 and a sector signal SECTOR, respectively.
The fourth NMOS transistor N14 is commonly connected to all of the decoding circuits 21_1 to 21_i in the decoding block 20_1 and the fifth NMOS transistor N15 is commonly attached to all of the decoding blocks 20_1 to 20_j. Further, a second PMOS transistor P12 is located between a first supply voltage node VPPX and a second node Q12 and operates in response to the potential of an output node WL1. A third PMOS transistor P13 is attached between the first supply voltage node VPPX and the output node WL1 and operates in response to the potential of the second node Q12.
A second NMOS transistor N12 is connected between the first node Q11 and the second node Q12 and always maintains a turned-on state since its gate is attached to the third supply voltage node Vcc. Finally, a third NMOS transistor N13 being a triple NMOS transistor is positioned between the output node WL1 and the second supply voltage node VEEX and its gate is connected to the first node Q11.
The flash memory device shown in FIG. 1A includes the multiplexor 30 that is separated into two parts, e.g., a first part for controlling the bit lines of the cells and a second part for controlling the source lines of the cells. The second part employs NMOS transistors positioned between the source lines, e.g., Source0 and Sourcek, and the ground node Vss, and operating in response to a source control signal SOCTRL.
An operational timing diagram of the conventional flash memory device shown in FIGS. 1A-1B is shown in FIG. 2. A method for programming the conventional flash memory device will be explained hereinafter with reference to the accompanying drawings.
If a program instruction, a program address and program data are inputted to the conventional flash memory device, the reset signal XRST is transited from a low state to a high state and the first predecoder signal XPREA1. The second predecoder signal XPREB0 and the sector signal SECTOR, which are selected by the program address, are also transited from a low state to a high state. Accordingly, the first PMOS transistor P11 is turned off in response to the reset signal XRST of the high state. In response to the second predecoder signal XPREB0 and the sector signal SECTOR having the high state, the fourth and the fifth NMOS transistors N14 and N15 are turned on. The potential of the first node Q11 is passed to the ground node Vss and the first node Q11 thus maintains a low state. Subsequently, in response to the potential of the first node Q11 maintaining the low state, the third NMOS transistor N13 is turned off and the second node Q12 also has a low state.
The third POMS transistor P13 is turned on in response to the potential of the second node Q12 having the low state and, the first supply voltage VPPX is thus provided to the output node WL1. Since the potential of the output node WL1 maintains the high voltage VPPX, the second PMOS transistor P12 is turned off. The first supply voltage VPPX, which is provided to the output node WL1 by a gate pump, ascends to a program voltage of about 9 V. At the same time, a bit line selected by the program address is transited from a low state to the program voltage by a drain pump. Accordingly, a programming operation for a selected cell A is executed. The source lines of all of the cells therefore maintain the ground potential Vss since the sixth and the seventh NMOS transistor N16 and N17 are turned on in response to the source control signal SOCTRL.
However, in the case of the conventional flash memory device performing the programming operation as described above, as a drain voltage of a cell ascends to the program voltage 5 V, a threshold voltage of an unselected cell decreases by the coupling with the drain voltage. As a result, a leakage current of the unselected cell increases and the required current for programming the selected cell is about twice that of a pure program current. This results in substantially increasing the size of the drain pump providing a current to the bit line of the selected cell. Further, as the bit line current of the selected cell increases, the drain voltage of the selected cell substantially decreases, and programming speed for a cell is diminished.
The present invention overcomes the shortcomings associated with the background art and achieves other advantages not realized by the background art.
An object of the present invention is to provide a flash memory device for increasing a threshold voltage of an unselected cell by providing a ground voltage to a source line of a selected cell and supplying a preset voltage to a source line of the unselected cell. The decrease of the threshold voltage of the unselected cell due to the drain coupling caused by a drain voltage supplied to a bit line of the selected cell is thereby compensated.
These and other objects are accomplished by a flash memory device comprising a flash memory cell array including a plurality of cellblocks, each cellblock having a multiplicity of cells; a multiplexor, the multiplexor selecting a bit line among a plurality of bit lines of the cell array; and decoding means, the decoding means supplying a program voltage to a word line selected among a plurality of word lines of the cell array based on a global word line signal, a local word line signal and a predecoder signal, providing a ground voltage to a source line of a cellblock including the selected word line in response to a sector program signal and an inverted sector program signal, and inputting a preset voltage higher than the ground voltage to source lines of unselected cellblocks.
These and other objects are further accomplished by a method of programming a flash memory device having a flash memory cell array including a plurality of cellblocks, each cellblock having a multiplicity of cells, a multiplexor, wherein the multiplexor selects a bit line among a plurality of bit lines of the cell array; and a decoding unit, the method comprising the steps of supplying a program voltage to a word line selected among a plurality of word lines of the cell array based on a global word line signal, a local word line signal and a predecoder signal, providing a ground voltage to a source line of a cellblock including the selected word line in response to a sector program signal and an inverted sector program signal, and inputting a preset voltage higher than the ground voltage to a plurality of source lines of unselected cellblocks.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. dr
The present invention will become more fully understood from the detailed description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
FIG. 1A is a schematic view of a flash memory device of the background art;
FIG. 1B is a schematic view of a flash memory device of the background art;
FIG. 2 is an operational timing diagram of the conventional flash memory device shown in FIGS. 1A-1B;
FIG. 3 is a schematic view of a flash memory device according to an embodiment of the present invention; and
FIG. 4 is an operational timing diagram of the flash memory device shown in FIG. 3.